Taylor & Francis Yoo, H: Low-Power NoC for High-Performance SoC Design

Designers are always challenged to interface various blocks within a system of chips to meet performance objectives while avoiding bottlenecks as more CPU and DSP cores are added. The efficient networking of various blocks is an on-going issue that is addressed by the authors of this practical work. Focusing on the real chip implementation of SoC by using NoC, they explore the latest techniques and compare industry-available solutions from both a technical and business perspective. While other works on this subject discuss theory, this volume shows readers how to design advanced ICs. It also teaches a new trend in IC design technology.